Intel's advanced packaging technology opens a whole new dimension for chip product architecture

Intel's advanced packaging technology opens a whole new dimension for chip product architecture

tenco 2019-07-11

At this week's SEMICON West conference in San Francisco, Intel engineering experts introduced the latest information on Intel's advanced packaging technologies and introduced a new range of foundational tools, including innovative ways to combine EMIB and Foveros technologies and new ODI (omni-directional Interconnect) technologies.Intel's new packaging technology will be integrated with its world-class manufacturing processes to help customers unleash innovation and move into a new era of computing.

Babak Sabi, vice President and general manager of package and test technology development at Intel corporation, said, "our vision is to use advanced technologies to package chips and small chips together to achieve the performance of single-chip system-level chips.Heterogeneous integration technology gives our chip architects unprecedented flexibility to mix and match IP and process technologies with different memory and I/O units in new diversified modules.Intel's vertically integrated architecture is unique in the era of heterogeneous integration, giving us unmatched power to simultaneously optimize architecture, process, and packaging to deliver leading products."

Chip packaging has always played a key role in electronic supply chain.As the physical interface between the processor and the motherboard, the package provides a landing zone for the chip's electrical signals and power supply.As the electronics industry moves toward a data-centric era, advanced packaging will play a bigger role than ever before.

Packaging is not only the last step in the manufacturing process, it is becoming a catalyst for product innovation.Advanced packaging technologies can integrate computing engines with multiple process processes to achieve performance similar to a single chip, but their platform range far exceeds the chip size limitations of a single chip integration.These technologies will greatly improve product-level performance and efficiency, reduce the area, and overhaul the system architecture.

As a leader in advanced packaging technology, Intel can provide both 2D and 3D packaging technology.At SEMICON West, Intel Shared three new technologies that will open a whole new dimension to chip product architecture.

Co-emib: Intel's EMIB (embedded multi-chip interconnection bridge) 2D packaging and Foveros 3D packaging technologies utilize high-density interconnection technology to achieve high bandwidth, low power consumption and competitive I/O density.Intel's new co-emib technology combines higher computational performance and power.The Co-EMIB can interconnect two or more Foveros components to achieve basically single chip performance.Designers are also able to connect simulators, memory, and other modules with very high bandwidth and very low power consumption.

ODI: Intel's new omni-directional interconnection technology (ODI) provides greater flexibility for omni-directional interconnection communication between packaged small and medium chips.The top chip can communicate horizontally with other small chips, as in EMIB technology, and vertically with the bottom bare chip through a silicon through-hole (TSV), as in Foveros technology.The ODI USES large vertical through-holes to provide power directly from the packaging substrate to the top bare plate. The large through-holes are much larger than traditional silicon through-holes and have lower resistance, thus providing more stable power transmission, while achieving higher bandwidth and lower delay through stacking.At the same time, this method reduces the number of silicon through-holes needed in the substrate, frees up more area for active transistors, and optimizes the size of bare chips.

MDIO: based on its advanced interface bus (AIB) physical layer interconnect technology, Intel has released a new bare chip interface technology called MDIO.MDIO technology supports the modular system design of small chip IP module library, which can provide higher energy efficiency and realize the response speed and bandwidth density of AIB technology more than twice.

Together, these new technologies add to Intel's powerful toolbox.They will combine with Intel's process technology to create a creative palette for chip architects, giving them the freedom to design innovative products.